#ifndef __UART_H__
#define __UART_H__

#include <rtthread.h>

#define CONFIG_SOC_DM646X
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	4 		/* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1		0x01c20000	/* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK		24000000	/* Input clock to NS16550 */
#define CONFIG_CONS_INDEX		1		/* use UART0 for console */
#define CONFIG_BAUDRATE			115200		/* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

typedef struct davinci_uart 
{
union
{
	volatile rt_uint32_t rhr;
	volatile rt_uint32_t thr;
	volatile rt_uint32_t dll;
}reg0;

union
{
	volatile rt_uint32_t ier;
	volatile rt_uint32_t dlh;
}reg1;

union
{
	volatile rt_uint32_t iir;
	volatile rt_uint32_t fcr;
	volatile rt_uint32_t efr;
}reg2;

	rt_uint32_t lcr;		/* 3 */

union
{
	volatile rt_uint32_t mcr;
	volatile rt_uint32_t xon1;
}reg4;

union
{
	volatile rt_uint32_t lsr;
	volatile rt_uint32_t xon2;
}reg5;

union
{
	volatile rt_uint32_t msr;
	volatile rt_uint32_t tcr;
	volatile rt_uint32_t xoff1;
}reg6;

union
{
	volatile rt_uint32_t spr;
	volatile rt_uint32_t tlr;
	volatile rt_uint32_t xoff2;
}reg7;

	rt_uint32_t mdr1;		/* 8 */
	rt_uint32_t mdr2;		/* 9 */

union
{
	volatile rt_uint32_t sflsr;
	volatile rt_uint32_t txfll;
}rega;

union
{
	volatile rt_uint32_t resume;
	volatile rt_uint32_t txflh;
}regb;

union
{
	volatile rt_uint32_t sfregl;
	volatile rt_uint32_t rxfll;
}regc;

union
{
	volatile rt_uint32_t sfregh;
	volatile rt_uint32_t rxflh;
}regd;

union
{
	volatile rt_uint32_t blr;
	volatile rt_uint32_t uasr;
}rege;

	rt_uint32_t acreg;		/* F */
	rt_uint32_t scr;		  /* 10*/
	rt_uint32_t ssr;		  /* 11*/
	rt_uint32_t eblr;	  /* 12*/
	rt_uint32_t reserved;/* 13*/	
	rt_uint32_t mvr;	    /* 14*/
	rt_uint32_t sysc;	  /* 15*/
	rt_uint32_t syss;	  /* 16*/
	rt_uint32_t wer;	    /* 17*/
  rt_uint32_t cfps;	  /* 18*/
}*davinci_uart_t;

/*
 * These are the definitions for the FIFO Control Register
 */
#define UART_FCR_FIFO_EN 	0x01 /* Fifo enable */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */

#define UART_FCR_RXSR		0x02 /* Receiver soft reset */
#define UART_FCR_TXSR		0x04 /* Transmitter soft reset */

/*
 * These are the definitions for the Modem Control Register
 */
#define UART_MCR_DTR	0x01		/* DTR   */
#define UART_MCR_RTS	0x02		/* RTS   */
#define UART_MCR_OUT1	0x04		/* Out 1 */
#define UART_MCR_OUT2	0x08		/* Out 2 */
#define UART_MCR_LOOP	0x10		/* Enable loopback test mode */

#define UART_MCR_DMA_EN	0x04
#define UART_MCR_TX_DFR	0x08

/*
 * These are the definitions for the Line Control Register
 *
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 */
#define UART_LCR_WLS_MSK 0x03		/* character length select mask */
#define UART_LCR_WLS_5	0x00		/* 5 bit character length */
#define UART_LCR_WLS_6	0x01		/* 6 bit character length */
#define UART_LCR_WLS_7	0x02		/* 7 bit character length */
#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
#define UART_LCR_STB	0x04		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define UART_LCR_PEN	0x08		/* Parity eneble */
#define UART_LCR_EPS	0x10		/* Even Parity Select */
#define UART_LCR_STKP	0x20		/* Stick Parity */
#define UART_LCR_SBRK	0x40		/* Set Break */
#define UART_LCR_BKSE	0x80		/* Bank select enable */
#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */

/*
 * These are the definitions for the Line Status Register
 */
#define UART_LSR_DR	0x01		/* Data ready */
#define UART_LSR_OE	0x02		/* Overrun */
#define UART_LSR_PE	0x04		/* Parity error */
#define UART_LSR_FE	0x08		/* Framing error */
#define UART_LSR_BI	0x10		/* Break */
#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
#define UART_LSR_TEMT	0x40		/* Xmitter empty */
#define UART_LSR_ERR	0x80		/* Error */

#define UART_MSR_DCD	0x80		/* Data Carrier Detect */
#define UART_MSR_RI	0x40		/* Ring Indicator */
#define UART_MSR_DSR	0x20		/* Data Set Ready */
#define UART_MSR_CTS	0x10		/* Clear to Send */
#define UART_MSR_DDCD	0x08		/* Delta DCD */
#define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
#define UART_MSR_DDSR	0x02		/* Delta DSR */
#define UART_MSR_DCTS	0x01		/* Delta CTS */

/*
 * These are the definitions for the Interrupt Identification Register
 */
#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */

#define UART_IIR_MSI	0x00	/* Modem status interrupt */
#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */

/*
 * These are the definitions for the Interrupt Enable Register
 */
#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */

/* useful defaults for LCR */
#define UART_LCR_8N1	0x03

void rt_hw_uart_init(void);

#endif
